Why Work With Adroitec Systems?
Adroitec Systems, believe that companies can innovate and deliver outstanding service only if they tap the commitment, energy, and imagination of their employees. As a member of our team you are valued for your efforts and career growth is driven entirely by your performance and not by your years of experience.
We will personally assist you in achieving your career goals with respect to our company values and work culture. Value for employees includes being treated respectfully and being involved in decision making. Employees also value meaningful work and excellent career opportunities.
Physical Design Engineer / Senior Engineer
Qualification Requirements
Required Skills & Knowledge:
4+ years of industry experience in the following technical areas:
- Physical design implementation (Floorplanning, CTS, and/or STA) in advanced technologies
- STA tool and timing closure methodologies
- Power grid, clock tree, and low-power reduction implementation methods
- Signal integrity and timing closure issues such as OCV/AOCV/POCV/Statistical Timing
- Physical Verification, Conformal Low Power (CLP), IR drop analysis, and Formal Verification
- Programming and scripting skills (Tcl, perl and/or C)
- Strong verbal and written communication skills
Education Requirements:
- Required : Bachelor's in Electronics and Communications Engineering, Electrical Engineering, and/or related field
- Preferred : Master's in VLSI, and/or related field
Location: Bangalore/ Hyderabad
DFT Engineers (DFT)
Qualification Requirements
Job Function:
Responsibilities include: Test strategy definition, DFT Architecture for large multi-core server chips, Logic specification and RTL design of DFT IP Software specification, DFT team leadership of related activities, ATPG test planning (including coverage, test time, test memory footprint on ATE Coordinates, cross-functional front-to- back SoC implementation and verification of DFT structures), and Bring-up of ATPG patterns on ATE.
Qualification Requirements:
3+ years of experience in the following technical areas :
- Defining and executing DFT-related tool flows, spanning insertion, ATPG, as well as DFT requirements in front-to- back SoC implementation flows
- Test vector planning for bring-up and production, and hand-on ATE bring-up experience
- Achieving high coverage via SAF, TDF, as well as knowledge of other techniques such as Small
Delay Defects, Path testing, LOC/LOS, etc. - Tessent, DFTC, TCL/PERL, IEEE 1149 and 1687, Primetime, SpyGlass, Verilog simulation including
SDF, and Advantest ATE - Architecting automation strategies that align with third party DFT tools and creating further efficiencies
- Leading large DFT/ATPG teams
- Defining/bring-up of DFT architecture including hierarchical core/chip based flows and pattern retargeting
- Experience with large device test on ATE and with architecting DFT strategies in support of multi-core and parallel testing
Education Requirements:
- Required : Bachelor's in Electronics and Communications Engineering, Electrical Engineering, and/or related field
- Preferred : Master's in VLSI, and/or related field
Location: Bangalore/ Hyderabad
Synthesis & STA engineers
Qualification Requirements
Job Function:
Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation. These candidates will create Power Intent for the designs and verify power intent on RTL, run static Low-Power checks on gate level netlists, Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams, run Power Analysis and estimate power at RTL level, run Sign off Power Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.
Qualification Requirements:
- Minimum 3 years of experience
- Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan
- Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
- Experience with Verilog and System Verilog
- RTL design experience with Perl/TCL/Makefile scripting
- Experience with Power Analysis using Power Artist and PTPX
- Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
Education Requirements:
- Required : Bachelor's in Electronics and Communications Engineering, Electrical Engineering, and/or related field
- Preferred : Master's in VLSI, and/or related field
Location: Bangalore/ Hyderabad