We provide Value-driven services such as complete Physical design flow, physical verification, DFT Services GDS Generation and Soc Integration. We focus on the use of the latest technology in the delivery of these services. Our team has expertise in advanced technology nodes including 7nm, 10nm, 14nm, 20nm, 22nm, 28nm, 45nm and 65nm, and has wide range of domain expertise in areas including wireless, networking, processors, and connectivity. Adroitec has capable to successfully deliverable of several multi-million gate SoCs in advanced
technology nodes.
Our strategic account management and results-based service delivery models are designed for client success.

Physical Design and Verification/STA Services

  • Floor planning, placement optimization
  • Power planning
  • CTS
  • Place and Route
  • Layout verification
  • Parasitic extraction and delay calculations
  • Tape out process flow
  • Expertise technology nodes 16nm, 28nm, 40nm, 60nm


  • Scan insertion, ATPG coverage analysis, Transition delay test coverage analysis
  • RTL and gate level simulation of scan and MBIST test vectors
  • SoC, Subsystem, IP level timing analysis
  • Methodology development for timing closure
  • Customized timing check for different IPs, Interfaces